The present invention relates to fuse structures for semiconductor devices. In one aspect, it relates to a programmable fuse structure for use in memory devices.
Redundancy in integrated circuit memories is part of many wafer and chip manufacturing strategies to improve yield. By providing redundant memory cells on memory chips for example, integrated circuit memory yields may be increased by eliminating from circuit operation the circuits or modules that are defective or that are not needed. The typical practice is to blow fuses or fray connections at fuses to alter the active cells or circuits, which allows redundant memory cells to be used in place of cells that are not functional. Such practice is often referred to as xe2x80x9cprogramming the fuses.xe2x80x9d
It is also common practice to use fuses to customize chips and modules after the production of the chip. Hence, one chip configuration may be used for multiply applications by programming the fuses (i.e., blowing or rupturing certain fuses) to deactivate selected circuit paths. Thus, a single integrated circuit design may be economically manufactured and adapted to a variety of custom uses.
Typically, fuses or fusible links are incorporated in an integrated circuit design, and then these fuses or fusible links are selectively blow or ruptured by passing an electrical current of sufficient magnitude through the selected fuses to cause them to melt and break the connection. A common design for such fuses is a fuse structure 20 having a straight link with a necked section 22, as shown in FIGS. 1 and 2, for example. The necked section 22 causes high current concentrations or xe2x80x9ccurrent crowdingxe2x80x9d where the dimensions of the fuse structure 20 are abruptly reduced at the necked section 22, which is sometimes referred to as the fuse link.
In the past fuses were often blown or ruptured by various means. But currently the preferred mechanism for opening the connection at the fuse is by electromigration because electromigration often provides more reliable and repeatable results than merely rupturing the link. Electromigration is the migration of atoms along the direction of electron flow (i.e., in the opposite direction of the current flow).
U.S. Pat. No. 5,420,456 discloses a z-shaped fuse structure, often referred to as a ZAG fuse, which uses a series of sharp angles (e.g., right angles) in the current path, like a chicane, to generate current crowding at the sharp corners. As the current tries to flow through the chicane-like structure, it crowds at the inside of the corners and generates heat in a very concentrated location. The increase in current density at these concentrated locations generates heat, which causes the fuse to melt open when a certain level of current is passed therethrough. Thus, instead of using a necked section, the ZAG fuses use a chicane section for obstructing the current flow and generating current crowding.
The necked fuses and ZAG fuses worked fine for prior circuits. However, because the patterning of circuit structures have shrunk to submicron levels in their dimensions, the width of the fuse links are now on the order of the grain size for the materials used in the fuses. Thus, there is much more fluctuation in the grain structures among the fuses, which results in variations in the resistance. It is desirable to have consistent resistance for a given fuse design so that the results of programming the fuses in a circuit are consistent. Therefore, as the dimensions of circuits have shrunk to the submicron levels, the prior ways of configuring a fuse structure are becoming less satisfactory due to the variations in resistances and inconsistencies among resulting fuse structures of the same design and dimensions. Hence, there is a need for a fuse structure that provides more consistent resistance for circuits being designed and produced at submicron levels.
In addition to circuits becoming smaller, the voltage and current levels for circuits also tend to decrease for reducing power consumption and to increase circuit speeds, for example. As voltage levels and current levels decrease for circuit designs, the voltage and current levels required to program fuses need to decrease as well, which often means a decrease in fuse structure dimensions. Hence, there is a need for a fuse structure that can be programmed at lower voltage and current levels, but without suffering from decreased resistance level consistency due to decreased dimensions.
Furthermore, the real estate on a chip continues to be a valuable commodity as the size of circuits and devices continue to shrink. Thus, there continues to be a need for fuse structures that use less real estate space on the chip. The ZAG design disclosed in U.S. Pat. No. 5,420,456 addresses this issue with its improved design. However, as the circuits continue to progress into submicron levels in size of components, the ZAG design will likely become less favorable because it will also suffer from the problem of inconsistent resistance due to the fuse structure dimensions being on the order of the grain structure for the fuse materials. Hence, there is a need for a fuse structure that can be programmed at lower voltage and current levels and that provides more consistent resistance values, as compared to existing fuse designs, while also being an efficient use of chip real estate space.
The problems and needs outlined above are addressed by certain aspects of the present invention. In accordance with one aspect of the present invention, a fuse structure formed in a semiconductor device is provided. The fuse structure includes a layer of fuse material, a first contact, and a second contact. The first contact has a first edge. At least a portion of the first edge abuts the fuse material layer. The second contact has a second edge. At least a portion of the second edge abuts the fuse material layer. The first edge faces the second edge. The first edge is separated from the second edge by a spaced distance. A conductive portion of the fuse material layer electrically connects between the first edge and the second edge within the spaced distance. The abutting portion of the first edge has a first length. The abutting portion of the second edge has a second length. The first length is greater than the second length.
In accordance with another aspect of the present invention, a programmable fuse structure formed in a semiconductor device is provided. The programmable fuse structure includes layer of fuse material, an anode contact, and a cathode contact. The layer of fuse material is substantially rectangular shaped. The anode contact at least partially borders a first area of the fuse material layer. The anode contact has an inner edge. At least a portion of the inner anode edge abuts the fuse material layer. The cathode contact is formed on the fuse material layer. The cathode contact covers a second area of the fuse material layer. The second area is at least partially surrounded by the first area of the fuse material layer. The cathode contact has an outer edge that faces at least part of the inner anode edge. At least a portion of the outer edge abuts the fuse material layer. The abutting portion of the outer cathode edge is separated from the abutting portion of the inner anode edge by a spaced distance. The abutting portion of the inner anode edge is electrically coupled to the abutting portion of the outer cathode edge via a conductive portion of the fuse material layer. The conductive portion of the fuse material layer is within the spaced distance.
In accordance with yet another aspect of the present invention, a fuse structure for use in a semiconductor device is provided. The fuse structure includes a layer of fuse material, an anode contact, and a cathode contact. The anode contact has a polygon-shaped outer edge and a polygon-shaped inner edge. At least a portion of the inner anode edge abuts the fuse material layer. The inner anode edge borders a first area of the fuse material layer. The abutting portion of the inner anode edge has a first length. The cathode contact has a polygon-shaped outer edge. The cathode contact is bordered by the first area of the fuse material layer. At least a portion of the outer cathode edge abuts the fuse material layer. The abutting portion of the outer cathode edge has a second length. The abutting portion of the inner anode edge is electrically coupled to the abutting portion of the outer cathode edge via a conductive portion of the fuse material layer within in the first area. The first length is greater than the second length.
In accordance with still another aspect of the present invention, a programmable fuse structure for use in a semiconductor device is provided. The programmable fuse structure includes a layer of fuse material, a first contact, and a second contact. The first contact has a first edge. At least a portion of the first edge abuts the fuse material layer. The abutting portion of the first edge has a first length. The second contact has a second edge. At least a portion of the second edge abuts the fuse material layer. The abutting portion of the second edge has a second length. A length across the fuse material layer along its upper surface in any direction is equal to or greater than the second length of the second contact. The first length is greater than the second length.
In accordance with another aspect of the present invention, a synchronous dynamic random access memory (SDRAM) device is provided. The SDRAM includes a memory array, a plurality of redundant memory cells, a clock circuitry, a row address buffer, a column address buffer, a decode circuitry, and a fuse circuit. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell includes a capacitor coupled in series with a transistor. Each redundant memory cell includes a capacitor coupled in series with a transistor. The row address buffer is coupled to receive data at a time related to a clock signal received at the clock circuitry. The column address buffer is coupled to receive data at a time related to a clock signal received at the clock circuitry. The decode circuitry is coupled to the row address buffer and/or the column address buffer. The decode circuitry is also coupled to the memory array and the plurality of redundant memory cells. The fuse circuit is coupled with the decode circuitry. The fuse circuit includes first and second contacts abutting a layer of fuse material. The first contact has a first edge facing an edge of the second contact. The abutting portion of the first contact edge has a first length and the abutting portion of the second edge has a second length. The first length is greater than the second length.